1. Field of the Invention
The present invention relates to a method of fabricating semiconductor device, and in particular, to a method of forming contacts or plugs in semiconductor device.
2. Background of the Related Art
Width of a wire and an unit cell area on a chip decrease as semiconductor device integration increases. Alignment tolerance between a gate and a contact hole, for example, that exposes an impurity region for a source/drain junction of a cell is important because it has a direct influence on an yield and allows little alignment error.
Self-Aligned Contact (SAC) is a related art technique to prevent misalignment between a gate and a contact hole due to the reduced cell area. SAC can form a contact hole exposing an impurity region without exposing a gate, despite misalignment. SAC forms a sidewall spacer and a capping insulating layer on the side and upper surfaces of the gate using an insulating substance having an etch selectivity different from an insulating interlayer. In SAC, the gate is not exposed in spite of misalignment because the etch selectivity between the insulating interlayer and the capping insulating layer or the sidewall spacer is high.
FIG. 1 is a diagram that shows a layout of a related, art semiconductor device. Referring to FIG. 1, a field insulating layer 102 is formed on a semiconductor substrate 100 to define an active area of a device. A plurality of word lines (gate lines) overlap the active area and the field insulating layer 102 and are formed in a direction perpendicular to the active area on the semiconductor substrate 100. In this case, a first cap insulating layer 108 and a sidewall spacer 112 are formed on an upper surface and at the side of the gate 106, respectively.
An impurity region 110 doped with impurity ions having a type opposite to the substrate 100 is formed in the active area around both sides of the gate 106 to be a source/drain region. A first insulating interlayer 114 having an etch selectivity different from that of the first cap insulating layer 108 and the sidewall spacer 112 is formed to cover the above structure on the semiconductor substrate 100. First contact holes 115 and 116 exposing the impurity region 110 are formed in the first insulating interlayer 114. The first contact holes 115 and 116 are formed in a self-aligned manner because of the etch selectivity between the first insulating interlayer 114 and the first cap insulating layer 108 or the sidewall spacer 112. The first contact hole 115 exposes a portion of the field insulating layer 102 as well as the impurity region 110. However, the other first contact hole 116 exposes only the impurity region 110. First plugs 118 and 119 are formed in the first contact holes 115 and 116 to contact the impurity region 110.
FIG. 2A to FIG. 2C are diagrams that show cross-sectional views of fabricating a related art semiconductor device in accordance with a cutting line Ixe2x80x94I in FIG. 1. FIG. 3 is a diagram that shows a three-dimensional view of a related art SAC process step. Referring to FIG. 2A, an active area is defined by forming a field insulating layer 102 in a P-typed semiconductor substrate 100 with a shallow trench isolation method (STI).
A gate oxide 104 is formed by thermally oxidizing an exposed portion of the semiconductor substrate 100. Silicon nitride and impurity-doped polycrystalline silicon are formed on the field insulating layer 102 and the gate oxide layer 104 by chemical vapor deposition (CVD).
The silicon nitride and polycrystalline silicon are patterned by photolithography. The polycrystalline silicon becomes a gate 106 and the silicon nitride becomes a first cap insulating layer 108. An impurity region 110 for a source/drain region is formed by implanting N-type impurities in the exposed portion of the active area on the semiconductor substrate 100 using the first cap insulating layer 108 as a mask.
Referring to FIG. 2B, a sidewall spacer 112 is formed at the sides of the gate 106 and the first cap insulating layer 108. The sidewall spacer 112 is formed by depositing an insulating substance having the same etch rate as the first cap insulating layer 108. Accordingly, silicon nitride or the like is deposited on a whole surface of the above structure and then, the insulating substance is etched with reactive ion etch (RIE) or the like to expose the impurity region 110.
A first insulating interlayer 114 is formed by either depositing silicon oxide such as Undoped Silicate Glass (USG), Phosphor Silicate Glass (PSG), Borophospho Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (FEOS) or the like or coating the semiconductor substrate 100 with Spin On Glass (SOG) to cover the first cap insulating layer 108 and the sidewall spacer 112. First contact holes 115 and 116, which expose the impurity region 110, are formed by patterning the first insulating layer 114 with photolithography. In this case, the contact holes may be formed by SAC as an etch rate of the first cap insulating layer 108 or the sidewall spacer 112 is different from that of the first insulating interlayer 114.
The first contact holes 115 and 116 are formed by coating the first insulating interlayer 114 with a photoresist 117, by patterning the photoresist 117 as shown in Pig. 3, and etching the first insulating interlayer 114 using the photoresist 117 as a mask. The first contact hole 115 is formed to expose both portions of the field insulating layer 102 and the impurity region 110, while the other first contact hole 116 is formed to expose only the impurity region 110.
Referring to FIG. 2C, polycrystalline silicon doped with impurities is deposited on the first insulating interlayer 114 by CVD to fill up the first contact holes 115 and 116. First plugs 118 and 119 are formed by etching back the polycrystalline silicon with a chemical-mechanical polishing (CMP) method to expose the first insulating interlayer 114. Thus, the first plugs 118 and 119 are only within the contact holes 115 and 116.
The first plug 118 contacts the impurity region 110 in the first contact hole 115 and also extends to the field insulating layer 102, while the other first plug 119 contacts the impurity region in the second contact hole 116. The extended part of the first plug 118, not shown in the drawing, contacts a bitline perpendicular to the gate 106 over the field region.
FIG. 4A to FIG. 4D are diagrams that show cross-sectional views of a related art method of fabricating a semiconductor device that carries out a process in a cell region CA1 and a peripheral region PA1 simultaneously. Reference numbers of identical elements in FIG. 2A to FIG. 2C are the same.
Referring to FIG. 4A, an active area of a device is defined by forming a field insulating layer 102 with an STI method in a P-type semiconductor substrate 100 having a cell region CA1 and a peripheral region PA1. A gate oxide 104 is formed by thermally oxidizing an exposed portion of the semiconductor substrate 100. Silicon nitride and polycrystalline silicon, which is doped with impurities, are formed on the field insulating layer 102 and the gate oxide layer 104 by CVD. The silicon nitride and polycrystalline silicon are patterned by photolithography. The polycrystalline silicon becomes gates 106 and 120 and the silicon nitride becomes a first cap insulating layer 108. An impurity region 110 for a source/drain region of a memory cell and a lightly-doped impurity region 122 for an lightly doped drain (LDD) of a driving cell are formed in the cell region CA1 and the peripheral region PA1, respectively, by implanting N-typed impurities lightly in the exposed portions of the active area on the semiconductor substrate 100 using the first cap insulating layer 108 as a mask. Referring to FIG. 4B, a sidewall spacer 112 is formed at the sides of the gate 106 and the first cap insulating layer 108. The sidewall spacer 112 is formed by depositing an insulating substance, which has the same etch rate as the first cap insulating layer 108, such as silicon nitride on a whole surface of the above structure. By etching back the insulating substance with a reactive ion etch (RIE) or the like, the impurity regions 110 and 122 are exposed.
The peripheral region PA1 is exposed by exposure and development after the semiconductor substrate 100 has been coated with photoresist 124. A heavily-doped impurity region 126 is formed by implanting N-typed impurities in an exposed portion of the peripheral region PA1 on the semiconductor substrate 100 using the photoresist 124 as a mask. The heavily-doped impurity region 126 overlaps the lightly-doped impurity region 122 and is used for a source/drain region of the driving cell.
A first insulating interlayer 114 is formed by either depositing silicon oxide such as USG, PSG, BPSG, TEOS or the like on the semiconductor substrate 100 or coating the semiconductor substrate 100 with SOG to cover the first cap insulating layer 108 and the sidewall spacer 112. The first contact holes 115 and 116 exposing the impurity region 110 in the cell region CA1 are formed by patterning the first insulating interlayer 114 with photolithography. The first contact hole 115 is formed to expose the field insulating layer 102 and the impurity region 110, while the other first contact hole 116 is formed to expose the impurity region 110. The first contact holes 115 and 116 may be formed by SAC as an etch rate of the first cap insulating layer 108 or the sidewall spacer 112 is different from that of the first insulating interlayer 114.
Referring to FIG. 4D, polycrystalline silicon doped with impurities is deposited on the first insulating interlayer 114 by CVD to fill the first contact holes 115 and 116. The first plugs 118 and 119 remain only inside the first contact holes 115 and 116. The first plugs 118 and 119 are formed by etching back the polycrystalline silicon by CMP to expose the first insulating interlayer 114. Accordingly, the first plug 118 contacts the impurity region 110 in the first contact hole 115 and extends to the field insulating layer 102, while the other first plug 119 contacts the second contact hole 116. The extended part of the first plug 118 over the field insulating layer 102 (not shown) contacts a bitline, which is perpendicular to the gate 106 over the field region.
FIG. 5A to FIG. 5D are diagrams that show cross-sectional views of another related art fabricating method for a semiconductor device, which begins after the step shown in FIG. 2C, and includes forming a second plug. The cross-sectional views in FIGS. 5A-5D correspond to cutting lines Ixe2x80x94I and IIxe2x80x94II in FIG. 1.
After the completion of the step in FIG. 2C, a second insulating interlayer 130 is formed by depositing silicon oxide by CVD on both of the first insulating interlayer 114 and the first plugs 118 and 119 as shown in FIG. 5A. Referring to FIG. 5B, the extended part of the first plug 118 to the field insulating layer 102 is exposed by patterning the second insulating interlayer 130 with photolithography. An electrically-conductive substance such as W etc. is deposited on the second insulating interlayer 130 to contact an exposed portion of the first plug 118. Then, an insulating substance having a different etch rate than the second insulating interlayer 130 such as silicon nitride or the like is deposited on the electrically-conductive substance of metal.
A second cap insulating layer 134 and a bitline 132 are successively formed by patterning the insulating substance and the electrically-conductive substance with photolithography. Thus, the bitline 132 and the second cap insulating layer 134 are formed along a direction perpendicular to the gate 106 over the field insulating layer 102.
Referring to FIG. 5C, a sidewall spacer 136 is formed at sides of the bitline 132 and the second cap insulating layer 134. The sidewall spacer 136 is formed by depositing an insulating substance such as silicon nitride etc. on the second insulating interlayer 130 to cover the second cap insulating layer 134 and etching back the insulating substance with RIE. A third insulating interlayer 138 is formed on the second insulating interlayer 130 to cover both the second cap insulating layer 134 and the sidewall spacer 136. A second contact hole 140 exposing the first plug 119 is formed by patterning the second and third insulating interlayers 130 and 138 with photolithography. The second contact hole may be formed by SAC because etch rates of the cap insulating layer 134 and the sidewall spacer 136 differ from those of the second and third insulating interlayers 130 and 138.
Referring to FIG. 5D, polycrystalline silicon doped with impurities is deposited on the third insulating interlayer 138 by CVD to fill the second contact holes 140. A second plug 142 is left only within the second contact hole 140 by etching back the polycrystalline silicon using CMP to expose the third insulating interlayer 138.
As described above, the related art methods of fabricating semiconductor devices have various disadvantages. The related art methods of forming semiconductor devices have a defect in that voids in the first plugs are formed because of a high aspect ratio of the first contact hole. Further, a thickness of the first insulating interlayer causes a problem in forming the first contact hole because the first insulating interlayer should be formed to cover the first cap insulating layer. In addition, it is difficult to expose small areas for forming the first and second contact holes of the first and second plugs in an exposure step, and the semiconductor substrate is damaged by the etch for the first contact hole. Moreover, the lightly-doped region is formed narrowly in the peripheral region. Since the sidewall spacers of the second gate in the peripheral region and the first gate in the cell region are formed in the same way, hot carriers can be generated for both from short channel effect.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the present invention is to provide a method of fabricating semiconductor device that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a method of fabricating semiconductor device in which an exposure step is less complicated and more rapidly performed because plugs are formed without contact holes.
Another object of the present invention is to provide a method of fabricating semiconductor device that prevents etch damage on a semiconductor substrate during plug DOS formation.
Another object of the present invention is to provide a method of fabricating semiconductor device that prevents the generation of hot carriers caused by the short channel effect.
Another object of the present invention is to provide a method of fabricating semiconductor device that prevents the generation of hot carriers caused by the short channel effect of a driving cell in a peripheral region.
To achieve at these and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a method of fabricating a semiconductor device according to the present invention includes the steps of defining an active area of device by forming a field insulating layer on a semiconductor substrate of a first conductive type, forming a gate oxide on an exposed surface of the active layer in the semiconductor substrate and forming a plurality of gates and a cap insulating layer in a direction perpendicular to the active area, forming an impurity region of a second conductive type in the exposed active area of the semiconductor substrate and forming a plurality of sidewall spacers at sides of the gates, forming an electrically-conductive layer to be contacted with the impurity region between the gates on the semiconductor substrate, forming a plurality of plugs by patterning the electrically-conductive layer wherein the plugs are contacted with the impurity region, and forming an insulating interlayer on a place where the plugs are not formed between the gates.
In another aspect, to further achieve at least the above objects in a whole or in parts, a method of forming a semiconductor device according to the present invention includes forming a semiconductor substrate of a first conductivity type, forming a plurality of gates along a first direction on the semiconductor substrate, forming impurity regions of a second conductive type in the substrate along sides of the gates, forming a plurality of sidewall spacers at the sides of the gates, forming a conductive layer that contacts the impurity regions adjacent the gates and forming a plurality of plugs by patterning the conductive layer.
To further achieve the above objects, a method of manufacturing a semiconductor device according to the present invention includes forming a semiconductor substrate of a first conductivity type having an active area, wherein the semiconductor substrate includes a cell region and a peripheral region, forming a plurality of gates along a first direction in the cell and peripheral regions, forming a first impurity region along at least one gate in the cell region and a second impurity region along at least one gate in the peripheral region, forming a first etch-stop layer covering both of the semiconductor substrate and the gates in the peripheral region and forming first sidewall spacers at sides of the gates in the cell region, forming a first conductive layer between the gates to contact the first impurity region in the cell region and on the etch-stop layer in the peripheral region, forming a plurality of plugs in the cell region by patterning the first conductive layer, wherein the plugs contact the first impurity region in the cell region, forming a second sidewall spacers at the sides of the at least one gate to expose the second impurity region in the peripheral region, wherein the second sidewall spacers includes the etch-stop layer, forming a heavily-doped impurity region in an exposed part of the second impurity region in the semiconductor substrate in the peripheral region, and forming an insulating interlayer between the gates where the plugs are not formed.
To further achieve the above objects, a method of manufacturing a semiconductor device according to the present invention includes forming a semiconductor substrate of a first conductivity type, defining an active area by forming a field insulating layer on the substrate, forming a plurality of gates along a first direction on the active area, each of the gates includes a gate oxide, a gate electrode on the gate oxide and a first cap insulating layer on the gate electrode, forming impurity regions of a second conductive type in an exposed area of the substrate in the active area along sides of the gates, forming a plurality of first sidewall spacers on the sides of the gates, forming a conductive layer to contact the impurity regions between the gates, forming a plurality of first plugs by patterning the conductive layer, wherein each of the first plugs contact a corresponding impurity region, wherein extended portions of some of the first plugs extend onto the field insulating layer, forming a first insulating interlayer where the first plugs are not formed between the gates, forming a second insulating interlayer on the first cap insulating layer to cover the first plugs and patterning the second insulating interlayer to expose at least one of the extended portions of the first plugs, forming a signal lines and a second cap insulating layer on the second insulating interlayer, wherein the signal lines contact the exposed portions of the first plugs, exposing the first plugs and forming second sidewalls at sides of the signal lines by etching the second insulating interlayer, and forming second plugs that contact the exposed first plugs.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.